Image sensors find applications in a wide variety of fields, including machine vision, robotics, astronomy, navigation, as well as consumer products. While complementary metal-oxide-semiconductor (CMOS) technology has provided the foundation for advances in low-cost, low-power, reliable, highly integrated systems for many consumer applications, charge coupled devices (CCDs) have been, until recently, the primary technology used in electronic imaging applications. CCDs, however, are high capacitance devices that require high voltage clocks, consume large amounts of power, provide only serial output, and require specialized silicon processing that is incompatible with CMOS technology.
The availability of sub-micron CMOS technology and the advent of active pixel sensors (APS) have made CMOS technology more attractive for imaging applications. Active pixel sensors have transistors within a pixel unit cell to provide amplification and use manufacturing processes that are compatible with CMOS processes. Small pixel sizes, low noise, high speed, and high dynamic range have been demonstrated in such CMOS imagers using a variety of designs. The expected scaling of MOS devices to even smaller geometries will improve the operation and application of CMOS-based integrated circuits, but such scaling can adversely affect the performance of imagers. For example, the scaling of MOS devices in imagers requires a continued increase in channel doping and lower operating voltages, thus leading to significantly reduced depletion widths on the order of less than 0.1 μm. Photoelectrons generated within a depletion region are efficiently collected while photoelectrons generated outside the depletion region are collected only inefficiently, and can diffuse into adjacent pixels. Because silicon has an indirect band gap, absorption lengths in silicon tend to be long.
For photons having a wavelength in the range of 400–800 nm, the photon absorption depth in silicon varies from about 0.1 μm to about 16 μm. For example, at a wavelength λ=700 nm, a silicon absorption constant α is about 3·103 cm2, corresponding to an absorption length α−1 of about 3.3 μm at room temperature. Even longer absorption lengths, as long as several hundred microns, are associated with photon wavelengths approaching the bandgap of silicon. However, the depth Xd of a depletion layer varies as Xd≈(2εsiΦ/eNA)1/2, wherein Φ is a depleting potential, NA is an acceptor concentration, εs is a permittivity of silicon, and e is electron charge. In a typical 0.5 μm CMOS technology, the depletion widths are less than 0.2 μm. With the exception of light at blue wavelengths, many photons in the visible spectrum are absorbed outside the depletion region. Therefore, CMOS imagers implemented using an unmodified sub-micron CMOS technology generally exhibit a lower quantum efficiency and increased cross-talk compared to imagers implemented with a lower resolution fabrication process. Increased cross-talk can lead to degraded color performance and smear.
The breakdown voltage of MOS structures limits the applied potential, and hence the use of high resistivity silicon (low NA) is required. Using a silicon charge collection region with low doping concentration (e.g., 2*1013/cm3), a 10-μm thick optical cavity can be fully depleted at about 1.8 volts. However, the low NA doping is most often incompatible with conventional CMOS processes.
Another problem in imagers made using bulk-CMOS technology is a rise in photodiode leakage current when exposed to radiation. This rise in leakage current is caused by the use of Local Oxidation of Silicon (LOCOS) processes to create isolation regions. For example, as shown in FIG. 7, an oxide isolation region 702 is configured to separate a photodiode and a MOSFET. A so-called “bird's beak” feature 704 at a transition between a thin-gate oxide region 706 and the isolation region 702 is associated with high electric fields, thereby causing increased trap-generation during exposure to radiation. Although using a radiation-hard fabrication process can reduce leakage currents, such processes are relatively expensive and add to the overall imager cost.
In contrast to bulk-CMOS technology, silicon-on-insulation (SOI) CMOS technologies use SOI wafers that include three layers, a single-crystal layer of silicon, upon which integrated circuits are fabricated, a base silicon substrate and a thin insulator that electrically insulates the single-crystal layer and the substrate. This thin insulator reduces parasitic capacitance typically associated with a circuit device and a substrate in conventional bulk processes. Such SOI process can produce devices that exhibit lower power consumption and higher processing speeds than conventional bulk devices. Device operation in SOI-based devices is similar to that of bulk devices, except that transistors and other circuit elements do not share a common substrate.
While SOI-MOS devices can provide several advantages over bulk-MOS devices, the thin silicon layer of such devices makes them unsuitable for imagers. In particular, the SOI silicon layers are too thin to efficiently absorb visible and near-infrared light. Pain and et al., U.S. Pat. No. 6,380,572 and Zhang et al., “Building Hybrid Active Pixels for CMOS Imager in SOI Substrate,” 1999 IEEE International SOI Conference (1991), disclose active pixel sensors in which photodetectors are formed in a bulk silicon substrate and circuit elements are formed in a SOI silicon layer that is separated from the bulk silicon by a buried oxide layer in a thin silicon film formed on an insulator layer disposed on the substrate. Such devices provide a thick charge collection region, but bulk silicon used for such SOI manufacturing generally is not suited for photodetector manufacture. Furthermore, bulk silicon is difficult to thin for back-illuminated operation. Conventional back-thinning processes require a back-surface implant and activation process that typically requires temperatures above 800° C. Thus, these thinning processes are incompatible with standard CMOS metallization processes, and require complex post-processing techniques that are generally difficult to control.
In view of these and other shortcomings, improved active pixel sensors and manufacturing processes for such sensors are needed.